Hello
Could you clarify more regarding the SDO pin? When is the SDO pin in tristate? What is the SDO pin state when the sync/ signal is in “high” level?
From the spec table we can see a tri-state situation:
Also in figure 6 in data sheet:
Seems like the SDO pin is in tri-state/Hi-Z when SYNC/ is High and active when Sync/ is low...
Please clarify.
Thanks